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september 2013 doc id 13329 rev 10 1/31 1 VNQ5050AK-E quad channel high side driver with analog current sense for automotive applications features general features: ? inrush current active management by power limitation ? very low standby current ? 3.0v cmos compatible input ? optimized electromagnetic emission ? very low electromagnetic susceptibility ? in compliance with the 2002/95/ec european directive diagnostic functions: ? proportional load current sense ? high current sense precision for wide current range ? current sense disable ? thermal shutdown indication ? very low current sense leakage protection: ? undervoltage shutdown ? overvoltage clamp ? load current limitation ? self limiting of fast thermal transients ? protection against loss of ground and loss of v cc ? thermal shutdown ? reverse battery protection (see figure 25 ) ? electrostatic discharge protection application all types of resistive, inductive and capacitive loads. suitable as led driver. description the VNQ5050AK-E is a monolithic device made using stmicroelectronics vipower m0-5 technology. it is intended for driving resistive or inductive loads with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). this device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when cs_dis is driven low or left open. when cs_dis is driven high, the current sense pin is in a high impedance condition. output current limitation protects the device in overload condition. in case of long overload duration, the device limits the dissipated power to a safe level up to thermal shutdown intervention. thermal shutdown with automatic restart allows the device to recover normal operation as soon as the fault condition disappears. parameters symbol value max supply voltage v cc 41 v operating voltage range v cc 4.5 to 36 v max on-state resistance (per ch.) r on 50 m current limitation (typ) i limh 19 a off-state supply current i s 2a (1) 1. typical value with all loads connected. powersso-24 table 1. device summary package order codes tube tape and reel powersso-24 VNQ5050AK-E vnq5050aktr-e www.st.com
contents VNQ5050AK-E 2/31 doc id 13329 rev 10 contents 1 block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 gnd protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20 3.1.1 solution 1: resistor in the ground line (rgnd only) . . . . . . . . . . . . . . . . 20 3.1.2 solution 2: a diode (dgnd) in the ground line. . . . . . . . . . . . . . . . . . . . 21 3.2 load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 microcontroller i/os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 maximum demagnetization energy (vcc = 13.5v) . . . . . . . . . . . . . . . . . 23 4 package and pc board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 powersso-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 ecopack? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 powersso-24? mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VNQ5050AK-E list of tables doc id 13329 rev 10 3/31 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. switching (v cc =13v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 8. current sense (8v list of figures VNQ5050AK-E 4/31 doc id 13329 rev 10 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. delay response time between rising edge of output current and rising edge of current sense (cs enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. i out /i sense vs i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10. off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 11. high level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 12. input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 15. input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 16. on-state resistance vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 17. on-state resistance vs v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 18. undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 19. turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 20. i limh vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 21. turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 22. cs_dis high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 23. cs_dis clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 24. cs_dis low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 25. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 26. waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 27. maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23 figure 28. powersso-24 pc board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 29. rthj-amb vs pcb copper area in open box free air condition (one channel on) . . . . . . . . . 24 figure 30. powersso-24 thermal impedance junction ambient single pulse (one channel on) . . . . . 25 figure 31. thermal fitting model of a double channel hsd in powersso-24 . . . . . . . . . . . . . . . . . . . 25 figure 32. powersso-24? package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 33. powersso-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 34. powersso-24 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VNQ5050AK-E block diagram and pin configuration doc id 13329 rev 10 5/31 1 block diagram and pin configuration figure 1. block diagram table 2. pin functions name function v cc battery connection output n power output gnd ground connection. must be reverse battery protected by an external diode/resistor network input n voltage controlled input pin with hysteresis, cmos compatible. controls output switch state current sense n analog current sense pin, delivers a current proportional to the load current cs_dis active high cmos compatible pin, to disable the current sense pin logic undervoltage overtemp. 1 i lim 1 pwclamp 1 i out1 gnd input1 v cc output1 current sense1 driver 1 v cc clamp v dslim 1 output2 current sense2 cs_dis input3 k 1 pwr lim 1 input2 input4 control & protection equivalent to channel1 input2 current v cc output3 input3 current v cc output4 input4 current v cc current sense3 current sense4 sense2 sense3 sense4 control & protection equivalent to channel1 control & protection equivalent to channel1
block diagram and pin configuration VNQ5050AK-E 6/31 doc id 13329 rev 10 figure 2. configuration diagram (top view) table 3. suggested connections for unused and not connected pins connection/pin current sense n.c. output input cs_dis floating n.r. (1) 1. not recommended. xx x x to ground through 1 k resistor xn.r. through 10 k resistor through 10 k resistor input2 current sense2 gnd v cc input1 current sense1 cs_dis. v cc current sense3 input3 input4 current sense4 output2 output2 output1 output1 output1 output2 output4 output4 output3 output3 output3 output4 tab = v cc
VNQ5050AK-E electrical specifications doc id 13329 rev 10 7/31 2 electrical specifications figure 3. current and voltage conventions note: v fn = v outn - v cc during reverse battery condition. 2.1 absolute maximum ratings stress values that exceed those listed in the ?absolute maximum ratings? table can cause permanent damage to the device. these are stress ratings only, and operation of the device at these, or any other conditions greater than those, indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. v fn i s i gnd v cc v cc outputn inputn v inn v sensen gnd cs_dis i csd v csd i inn current s ensen v outn i outn i sensen table 4. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 41 v -v cc reverse dc supply voltage 0.3 v - i gnd dc reverse ground pin current 200 ma i out dc output current internally limited a - i out reverse dc output current 20 a i in dc input current -1 to 10 ma i csd dc current sense disable input current -1 to 10 ma -i csense dc reverse cs pin current 200 ma v csense current sense maximum voltage v cc -41 +v cc v v e max maximum switching energy (single pulse) (l=3 mh; r l =0 ; v bat =13.5 v; t jstart =150 oc; i out = i liml (typ.)) 104 mj
electrical specifications VNQ5050AK-E 8/31 doc id 13329 rev 10 2.2 thermal data v esd electrostatic discharge (human body model: r=1.5k ; c=100pf) ? input ? current sense ? cs_dis ?output ?v cc 4000 2000 4000 5000 5000 v v v v v v esd charge device model (cdm-aec-q100-011) 750 v t j junction operating temperature -40 to 150 c t stg storage temperature -55 to 150 c table 4. absolute maximum ratings (continued) symbol parameter value unit table 5. thermal data symbol parameter max value unit r thj-case thermal resistance junction-case (with one channel on) 2.8 c/w r thj-amb thermal resistance junction-ambient see figure 29 c/w
VNQ5050AK-E electrical specifications doc id 13329 rev 10 9/31 2.3 electrical characteristics values specified in this section are for 8 v electrical specifications VNQ5050AK-E 10/31 doc id 13329 rev 10 table 8. current sense (8v VNQ5050AK-E electrical specifications doc id 13329 rev 10 11/31 i senseh analog sense output current in over temperature condition v cc = 13 v; v sense = 5 v - 8 - ma t dsense1h delay response time from falling edge of cs_dis pin v sense <4 v, 0.5 a electrical specifications VNQ5050AK-E 12/31 doc id 13329 rev 10 figure 4. current sense delay characteristics table 10. logic input symbol parameter test conditions min. typ. max. unit v il input low level voltage - - 0.9 v i il low level input current v in = 0.9 v 1 - - a v ih input high level voltage 2.1 - - v i ih high level input current v in = 2.1 v - - 10 a v i(hyst) input hysteresis voltage 0.25 - - v v icl input clamp voltage i in = 1 ma i in = -1 ma 5.5 -0.7 7v v v csdl cs_dis low level voltage - - 0.9 v i csdl low level cs_dis current v csd =0.9 v 1 - - a v csdh cs_dis high level voltage 2.1 - - v i csdh high level cs_dis current v csd =2.1 v - - 10 a v csd(hyst) cs_dis hysteresis voltage 0.25 - - v v cscl cs_dis clamp voltage i csd = 1 ma i csd = -1 ma 5.5 -0.7 7v v sense current input load current cs_dis t dsense2h t dsense2l t dsense1l t dsense1h
VNQ5050AK-E electrical specifications doc id 13329 rev 10 13/31 figure 5. delay response time between rising edge of output current and rising edge of current sense (cs enabled) figure 6. switching characteristics v in i out i sense i outmax i sensemax 90% i sensemax 90% i outmax t dsense2h t t t v out dv out /dt (on) t r 80% 10% t f dv out /dt (off) t d(off) t d(on) input t t 90% t won t woff
electrical specifications VNQ5050AK-E 14/31 doc id 13329 rev 10 figure 7. i out /i sense vs i out figure 8. maximum current sense ratio drift vs load current note: parameter guaranteed by design; it is not tested. 1000 1200 1400 1600 1800 2000 2200 2400 2600 1 1,5 2 2,5 3 3,5 4 4,5 5 i out (a) i out / i sense max tj = -40 c to 150 c max tj = 25 c to 150 c min tj = 25 c to 150 c min tj = -40 c to 150 c typical value -15 -10 -5 0 5 10 15 11,522,533,54 i out (a) dk/k(%)
VNQ5050AK-E electrical specifications doc id 13329 rev 10 15/31 figure 9. output voltage drop limitation table 11. truth table conditions input output sense (v csd =0 v) (1) 1. if the v csd is high, the sense output is at a high impedance, its potential depends on leakage currents and external circuit. normal operation l h l h 0 nominal over temperature l h l l 0 v senseh undervoltage l h l l 0 0 short circuit to gnd (rsc 10 m ) l h h l l l 0 0 if t j < t tsd v senseh if t j > t tsd short circuit to v cc l h h h 0 < nominal negative output voltage clamp l l 0 von iout vcc-vout tj=150 o c tj=25 o c tj=-40 o c von/ron(t)
electrical specifications VNQ5050AK-E 16/31 doc id 13329 rev 10 table 12. electrical transient requirements (part 1/3) iso 7637-2: 2004(e) test pulse test levels number of pulses or test times burst cycle/pulse repetition time delays and impedance iii iv 1 -75 v -100 v 5000 pulses 0.5 s 5 s 2 ms, 10 2a +37 v +50 v 5000 pulses 0.2 s 5 s 50 s, 2 3a -100 v -150 v 1h 90 ms 100 ms 0.1 s, 50 3b +75 v +100 v 1h 90 ms 100 ms 0.1 s, 50 4 -6 v -7 v 1 pulse - 100 ms, 0.01 5b (2) +65 v +87 v 1 pulse - 400 ms, 2 table 13. electrical transient requirements (part 2/3) iso 7637-2: 2004(e) test pulse test level results (1) 1. the above test levels must be considered referred to v cc = 13.5v except for pulse 5b. iii iv 1c c 2a c c 3a c c 3b c c 4c c 5b (2) 2. valid in case of external load dum p clamp: 40v maximum referred to ground. cc table 14. electrical transient requirements (part 3/3) class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
VNQ5050AK-E electrical specifications doc id 13329 rev 10 17/31 2.4 electrical characteristics curves figure 10. off-state output current figure 11. high level input current figure 12. input clamp voltage figure 13. input low level figure 14. input high level figure 15. input hysteresis voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 iloff (ua) off state vcc=13v vin=vout=0v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 iih (ua) vin=2.1v -50 -25 0 25 50 75 100 125 150 175 tc ( c) 5 5.2 5.4 5.6 5.8 6 6.2 6.4 6.6 6.8 7 vicl (v) iin=1ma -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.5 1 1.5 2 2.5 3 3.5 4 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 vhyst (v)
electrical specifications VNQ5050AK-E 18/31 doc id 13329 rev 10 figure 16. on-state resistance vs t case figure 17. on-state resistance vs v cc figure 18. undervoltage shutdown figure 19. turn-on voltage slope figure 20. i limh vs t case figure 21. turn-off voltage slope -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 10 20 30 40 50 60 70 80 90 100 ron (mohm) iout=2a vcc=13v 0 5 10 15 20 25 30 35 40 vcc (v) 0 10 20 30 40 50 60 70 80 90 100 ron (mohm) tc=-40c tc=25c tc=125c tc=150c -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 2 4 6 8 10 12 14 16 vusd (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 100 200 300 400 500 600 700 800 900 1000 (dvout/dt)on (v/ms) vcc=13v rl=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc ( c) 5 7.5 10 12.5 15 17.5 20 22.5 25 ilimh (a) vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 100 200 300 400 500 600 700 800 900 1000 (dvout/dt)off (v/ms) vcc=13v rl=6.5ohm
VNQ5050AK-E electrical specifications doc id 13329 rev 10 19/31 figure 22. cs_dis high level voltage figure 23. cs_dis clamp voltage figure 24. cs_dis low level voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 0.5 1 1.5 2 2.5 3 3.5 4 vcsdh (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 4 4.5 5 5.5 6 6.5 7 7.5 8 vcsdcl (v) icsd=1ma -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.5 1 1.5 2 2.5 3 3.5 4 vcsdl (v)
application information VNQ5050AK-E 20/31 doc id 13329 rev 10 3 application information figure 25. application schematic note: channel 2, 3, 4 have the same internal circuit as channel 1. 3.1 gnd protection network against reverse battery 3.1.1 solution 1: resistor in the ground line (r gnd only) this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1. r gnd 600 mv / (i s(on)max ). 2. r gnd (? v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsds. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not shared by the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how many devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then st suggests to utilize solution 2 (see below). v cc gnd output d gnd r gnd d ld c +5v v gnd cs_dis iinput r prot r prot current sense r prot r sense c ext
VNQ5050AK-E application information doc id 13329 rev 10 21/31 3.1.2 solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd = 1 k ) should be inserted in parallel to d gnd if the device drives an inductive load. this small signal diode can be safely shared amongst several different hsds. also in this case, the presence of the ground network will produce a shift ( 600mv) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. this shift will not vary if more than one hsd shares the same diode/resistor network. 3.2 load dump protection d ld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the v cc max dc rating. the same applies if the device is subject to transients on the v cc line that are greater than the ones shown in the iso t/r 7637/1 table. 3.3 microcontroller i/os protection if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of c and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of c i/os. -v ccpeak /i latchup r prot (v oh c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100 v and i latchup 20 ma; v oh c 4.5 v 5k r prot 180 k . recommended values: r prot = 10 k , c ext = 10 nf .
application information VNQ5050AK-E 22/31 doc id 13329 rev 10 figure 26. waveforms sense current input normal operation undervoltage v cc v usd v usdhyst input sense current load current load current overload operation input sense current t tsd t r t j load current input load voltage sense current load current VNQ5050AK-E application information doc id 13329 rev 10 23/31 3.4 maximum demagnetization energy (v cc =13.5v) figure 27. maximum turn-off current versus inductance (for each channel) note: values are generated with r l =0 . in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves a and b. demagnetization demagnetization demagnetization t v in , i l c: t jstart = 125c repetitive pulse a: t jstart = 150c single pulse b: t jstart = 100c repetitive pulse 1 10 100 0,1 1 10 100 l (mh) i (a) a b c
package and pc board thermal data VNQ5050AK-E 24/31 doc id 13329 rev 10 4 package and pc board thermal data 4.1 powersso-24 thermal data figure 28. powersso-24 pc board note: layout condition of r th and z th measurements (pcb: double layer, thermal vias, fr4 area= 77 mm x 86 mm, pcb thickness=1.6mm, cu thickness=70 m (front and back side), copper areas: from minimum pad lay-out to 8 cm 2 ). figure 29. r thj-amb vs pcb copper area in open box free air condition (one channel on) 30 35 40 45 50 55 0246810 rthj_amb(c/w) pcb cu heatsink area (cm^2)
VNQ5050AK-E package and pc board thermal data doc id 13329 rev 10 25/31 figure 30. powersso-24 thermal impedance junction ambient single pulse (one channel on) figure 31. thermal fitting model of a double channel hsd in powersso-24 (a) a. the fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cyc ling during thermal shutdown) are not triggered. 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (c/w) footprint 8 cm 2 2 cm 2
package and pc board thermal data VNQ5050AK-E 26/31 doc id 13329 rev 10 equation 1: pulse calculation formula where = t p /t table 15. thermal parameters area/island (cm 2 ) footprint 2 8 r1=r7=r9=r11 (c/w) 0.4 - - r2=r8=r10=r12 (c/w) 2 - - r3 (c/w) 6 - - r4 (c/w) 7.7 - - r5 (c/w) 9 9 8 r6 (c/w) 28 17 10 c1=c7=c9=c11 (w.s/c) 0.001 - - c2=c8=c10=c12 (w.s/c) 0.0022 - - c3 (w.s/c) 0.025 - - c4 (w.s/c) 0.75 - - c5 (w.s/c) 1 4 9 c6 (w.s/c) 2.2 5 17 z th r th z thtp 1 ? () + ? =
VNQ5050AK-E package and packing information doc id 13329 rev 10 27/31 5 package and packing information 5.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com . ecopack? is an st trademark. 5.2 powersso-24? mechanical data table 16. powersso-24? mechanical data symbol millimeters min. typ. max. a- -2.45 a2 2.15 - 2.35 a1 0 - 0.10 b0.33- 0.51 c0.23-0.32 d 10.10 - 10.50 e7.4 - 7.6 e-0.8- e3 - 8.8 - g- -0.1 g1 - - 0.06 h 10.1 - 10.5 h- -0.4 k0-8 l0.55- 0.85 n- -10o x4.1 - 4.7 y6.5 - 7.1
package and packing information VNQ5050AK-E 28/31 doc id 13329 rev 10 figure 32. powersso-24? package dimensions
VNQ5050AK-E package and packing information doc id 13329 rev 10 29/31 5.3 packing information figure 33. powersso-24 tube shipment (no suffix) figure 34. powersso-24 tape and reel shipment (suffix ?tr?) a c b all dimensions are in mm. base q.ty 49 bulk q.ty 1225 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 100 t (max) 30.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.05) 1.55 hole diameter d1 (min) 1.5 hole position f ( 0.1) 11.5 compartment depth k (max) 2.85 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
revision history VNQ5050AK-E 30/31 doc id 13329 rev 10 6 revision history table 17. document revision history date revision changes 14-sep-2004 1 initial release. 12-jan-2006 2 major general update. 9-mar-2007 3 reformatted and restructured. added contents, lists of tables and list of figures. added section 3.4: maximum demagnetization energy (vcc = 13.5v) . added ecopack? packages information. added new disclaimer. 22-aug-2007 4 figure 14: input high level and figure 15: input hysteresis voltage corrected. 01-oct-2007 5 table 4: absolute maximum ratings : changed e max value from 51 to 104 mj. table 8: current sense (8v VNQ5050AK-E doc id 13329 rev 10 31/31 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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